1. Field of the Invention
The invention relates to integrated circuit (xe2x80x9cICxe2x80x9d) packaging, in particular to dies and IC assemblies using underfill.
2. Related Art
Flip chips are surface-mounted chips having connecting metal lines attached to pads on the underside of the chips. A chip or die is typically mounted on an IC substrate to form an IC assembly. For example, a flip chip may be mounted on a package substrate and the resulting package mounted on a printed circuit board (xe2x80x9cPCBxe2x80x9d). A flip chip may also be directly mounted to a PCB.
Underfill is provided between the chip and the IC substrate to support the electrical connections, to protect them from the environment, and to reduce the thermomechanical stress on the flip chip connection. Underfill materials generally have different coefficients of thermal expansion (xe2x80x9cCTExe2x80x9d) from chip and substrate components, e.g., solder connections. This CTE mismatch can lead to thermomechanical stresses that can cause device failure. To avoid this problem, it is desirable for the underfill and other components to have similar CTEs. Underfill CTE may be adjusted by blending filler materials into the underfill. However, dispensing underfill involves long throughput time and acts as a bottleneck in the assembly process. If an underfill has high filler content, it may be difficult to distribute the underfill in a capillary or dispense flow process, especially when a small gap separates the chip and the substrate.
In conventional xe2x80x9cno flowxe2x80x9d underfill processes, underfill is applied to the surface of an IC substrate. To join a die to the substrate, the die""s flip chip bumps are pushed through the underfill material until the flip chip bumps make contact with corresponding package substrate bumps. FIG. 1 shows a cross-section of a die and package in a conventional no flow underfill process. Flip chip die 110 contains a plurality of flip chip bumps on a surface 112, one of which is shown as bump 115. The die 110 is mated to package substrate 120, which contains substrate bump 130 on substrate bump pad 125. A layer of solder resist 140 and a layer of filled underfill 135 cover substrate 120. Die 110 is joined to substrate 120 by pressing flip chip bump 115 through underfill 135 until flip chip bump 115 makes contact with substrate bump 130. This process can also occur at the wafer level, where the wafer contains a plurality of dies 110 each having a plurality of flip chip bumps 115. Package substrate 120 would then be part of a panel or sheet containing many substrate pads 125 and bumps 130 configured to mate with the flip chip bumps 115 on the wafer.
Such a no flow process normally results in high open fails, because filler particles are trapped between the flip chip bumps 115 and the substrate bumps 130. Reducing or eliminating filler in the underfill used in the no flow underfill process is a poor solution to this problem, because doing so restores the problem of poor reliability of the resulting products due to CTE mismatch.
There is therefore a need for an improved process for applying underfill in making IC assemblies.